[all-commits] [llvm/llvm-project] 764820: [RISCV][POC] Model frm control for vfadd

[Yueh-Ting (eop) Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 76482078cdd2dca1f553904a1d2092626ba12856
      https://github.com/llvm/llvm-project/commit/76482078cdd2dca1f553904a1d2092626ba12856
  Author: eopXD <yueh.ting.chen at gmail.com>
  Date:   2023-07-13 (Thu, 13 Jul 2023)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    M clang/include/clang/Basic/riscv_vector_common.td
    M clang/include/clang/Support/RISCVVIntrinsicUtils.h
    M clang/lib/Sema/SemaChecking.cpp
    M clang/lib/Sema/SemaRISCVVectorLookup.cpp
    M clang/lib/Support/RISCVVIntrinsicUtils.cpp
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfadd-out-of-range.c
    M clang/utils/TableGen/RISCVVEmitter.cpp
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
    M llvm/lib/Target/RISCV/RISCVInstrFormats.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
    M llvm/test/CodeGen/RISCV/rvv/combine-vmv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmf.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
    M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
    M llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll
    M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

  Log Message:
  -----------
  [RISCV][POC] Model frm control for vfadd

Depends on D152879.

Specification PR: riscv-non-isa/rvv-intrinsic-doc#226

This patch adds variant of `vfadd` that models the rounding mode control.
The added variant has suffix `_rm` appended to differentiate from the
existing ones that does not alternate `frm` and uses whatever is inside.

The value `7` is used to indicate no rounding mode change. Reusing the
semantic from the rounding mode encoding for scalar floating-point
instructions.

Additional data member `HasFRMRoundModeOp` is added so we can append
`_rm` suffix for the fadd variants that models rounding mode control.

Additional data member `IsRVVFixedPoint` is added so we can define
pseudo instructions with rounding mode operand and distinguish the
instructions between fixed-point and floating-point.

Reviewed By: craig.topper, kito-cheng

Differential Revision: https://reviews.llvm.org/D152996