[all-commits] [llvm/llvm-project] 56e60b: TargetLowering: fix an infinite DAG combine in Sim...

[Jon Roelofs via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 56e60bc5bbfb8fdf2b22a897e8801c87771c84e8
      https://github.com/llvm/llvm-project/commit/56e60bc5bbfb8fdf2b22a897e8801c87771c84e8
  Author: Jon Roelofs <jonathan_roelofs at apple.com>
  Date:   2023-07-12 (Wed, 12 Jul 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    A llvm/test/CodeGen/AArch64/arm64-setcc-swap-infloop.ll

  Log Message:
  -----------
  TargetLowering: fix an infinite DAG combine in SimplifySETCC

TargetLowering::SimplifySetCC wants to swap the operands of a SETCC to
canonicalize the constant to the RHS. The bug here was that it did so whether
or not the RHS was already a constant, leading to an infinite loop.

rdar://111847838

Divverential revision: https://reviews.llvm.org/D155095

This reverts commit cdc633e4bc93d4bf241ecd4c29691ae065749313.