[all-commits] [llvm/llvm-project] d43ccf: [RISCV] Split scheduler class for integer min/max ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d43ccffdc7f5c27c8db9722fe2ce7a61fb72595d
      https://github.com/llvm/llvm-project/commit/d43ccffdc7f5c27c8db9722fe2ce7a61fb72595d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-07-12 (Wed, 12 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV] Split scheduler class for integer min/max reduction from other integer reductions. NFC

Our downstream needs to give different scheduling for min/max from
other reductions.

Reviewed By: michaelmaitland

Differential Revision: https://reviews.llvm.org/D155108


  Commit: 40779e840062eafcfee7b16e28bc600ebf12ac3a
      https://github.com/llvm/llvm-project/commit/40779e840062eafcfee7b16e28bc600ebf12ac3a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-07-12 (Wed, 12 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

  Log Message:
  -----------
  [RISCV] Correct even register check for amocas.

We were checking that the encoding within our internal list of
registers was even. This worked today because X0 happens to have
an even value in that enum. This can break if any registers are
added before X0.

The correct check is to make sure it has an even offset from X0.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D155104


Compare: https://github.com/llvm/llvm-project/compare/0a6dfd40a659...40779e840062