[all-commits] [llvm/llvm-project] 58d1ea: [CodeGen] Store SP adjustment in MachineBasicBlock...

[Jay Foad via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 58d1eaa3b6ce4f7285c51f83faff7a3ac374c746
      https://github.com/llvm/llvm-project/commit/58d1eaa3b6ce4f7285c51f83faff7a3ac374c746
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2023-07-12 (Wed, 12 Jul 2023)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineBasicBlock.h
    M llvm/lib/CodeGen/MIRParser/MILexer.cpp
    M llvm/lib/CodeGen/MIRParser/MILexer.h
    M llvm/lib/CodeGen/MIRParser/MIParser.cpp
    M llvm/lib/CodeGen/MachineBasicBlock.cpp
    M llvm/lib/CodeGen/PrologEpilogInserter.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.h
    M llvm/test/CodeGen/ARM/2013-06-03-ByVal-2Kbytes.ll
    M llvm/test/CodeGen/MIR/Generic/basic-blocks.mir
    M llvm/tools/llvm-reduce/ReducerWorkItem.cpp

  Log Message:
  -----------
  [CodeGen] Store SP adjustment in MachineBasicBlock. NFCI.

Record the SP adjustment on entry to each basic block. This is almost
always zero except on targets like ARM which can split a basic block in
the middle of a call sequence.

This simplifies PEI::replaceFrameIndices which previously had to visit
basic blocks in a specific order and had special handling for
unreachable blocks. More importantly it paves the way for an equally
simple implementation of a backwards version of replaceFrameIndices,
which is required to fully convert PrologEpilogInserter to backwards
register scavenging, which is preferred because it does not rely on
accurate kill flags.

Differential Revision: https://reviews.llvm.org/D154281