[all-commits] [llvm/llvm-project] 309622: [RISCV] Fix name mangling for LMUL!=1 vector types...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 30962268e7a559d8714cca4d1af742915c9d29b1
      https://github.com/llvm/llvm-project/commit/30962268e7a559d8714cca4d1af742915c9d29b1
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-07-11 (Tue, 11 Jul 2023)

  Changed paths:
    M clang/lib/AST/ItaniumMangle.cpp
    M clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
    M clang/test/CodeGenCXX/riscv-rvv-fixedtypeinfo.cpp

  Log Message:
  -----------
  [RISCV] Fix name mangling for LMUL!=1 vector types with attribute(rvv_vector_bits)

We were always printing "m1", we need to calculate the correct LMUL instead.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D153659