[all-commits] [llvm/llvm-project] 11051d: [RISCV] Constrain register class before replaceReg...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 11051d7d864bc4afdb9ec85b20825fcbf5a40022
      https://github.com/llvm/llvm-project/commit/11051d7d864bc4afdb9ec85b20825fcbf5a40022
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-07-11 (Tue, 11 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp

  Log Message:
  -----------
  [RISCV] Constrain register class before replaceRegWith in RISCVMergeBaseOffset.

The register being replaced might have a more restrictive register
class due to requirements of the using instruction. We should
constrain the register class to preserve any restrictions.

This was found in our downstream on a custom instruction. I don't
have a test case for upstream currently.

Differential Revision: https://reviews.llvm.org/D154920