[all-commits] [llvm/llvm-project] 99809f: [RISCV] Simplify the definitions of interrupt CSRs

Wang Pengcheng via All-commits all-commits at lists.llvm.org
Mon Jul 10 20:21:03 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 99809f43779f0367256311ea6e4f87414fc9e896
  Author: wangpc <wangpengcheng.pp at bytedance.com>
  Date:   2023-07-11 (Tue, 11 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVCallingConv.td
    M llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
    M llvm/test/CodeGen/RISCV/interrupt-attr.ll

  Log Message:
  [RISCV] Simplify the definitions of interrupt CSRs

For `CSR_Interrupt`, we can generate the register list via a single

For `CSR_XLEN_F32_Interrupt` and `CSR_XLEN_F64_Interrupt`, I don't
see the reason why we need to keep the order the same as how we used
to allocate registers (and we have changed the order in D146488), so
I fold them into one `sequence`.

There are some *.ll changes because of the order change.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D154837

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