[all-commits] [llvm/llvm-project] dbd47c: [RISCV] Don't allow X0 to be used for 'r' constrai...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dbd47c4489b1680b0753c30745588c6248a8b448
      https://github.com/llvm/llvm-project/commit/dbd47c4489b1680b0753c30745588c6248a8b448
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-07-10 (Mon, 10 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/inline-asm.ll

  Log Message:
  -----------
  [RISCV] Don't allow X0 to be used for 'r' constraint in inline assembly

Some instructions treat x0 as a special encoding rather than as a
value of 0. Since we don't parse the inline assembly to know what
the instruction is, chooser the safest option of never using x0.

Fixes #63747.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D154744