[all-commits] [llvm/llvm-project] 29f630: [RISCV][MC] MC layer support for the experimental ...

Alex Bradbury via All-commits all-commits at lists.llvm.org
Mon Jul 10 00:27:16 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 29f630a1ddcbb03caa31b5002f0cbc105ff3a869
  Author: Alex Bradbury <asb at igalia.com>
  Date:   2023-07-10 (Mon, 10 Jul 2023)

  Changed paths:
    M clang/test/Preprocessor/riscv-target-features.c
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/MC/RISCV/attribute-arch.s
    A llvm/test/MC/RISCV/rv32zacas-invalid.s
    A llvm/test/MC/RISCV/rv32zacas-valid.s
    A llvm/test/MC/RISCV/rv64zacas-invalid.s
    A llvm/test/MC/RISCV/rv64zacas-valid.s

  Log Message:
  [RISCV][MC] MC layer support for the experimental zacas extension

This implements the v1.0-rc1 draft extension.

amocas.d on RV32 and amocas.q have the restriction that rd and rs2 must
be even registers. I've opted to implement this restriction in
RISCVAsmParser::validateInstruction even though for codegen we'll need a
new register class and can then remove this validation. This also
sidesteps, for now, the issue of amocas.d being different on rv32 vs

See <https://github.com/riscv-non-isa/riscv-c-api-doc/issues/37> for the
issue of needing an agreed asm register constraint for register pairs.

Differential Revision: https://reviews.llvm.org/D149248

More information about the All-commits mailing list