[all-commits] [llvm/llvm-project] 9c4aa8: [RISCV][TableGen] Remove f32 from XLenFVT for RV32.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9c4aa85ec18833a25141d1563f579ef9099d6eb9
      https://github.com/llvm/llvm-project/commit/9c4aa85ec18833a25141d1563f579ef9099d6eb9
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-07-05 (Wed, 05 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  [RISCV][TableGen] Remove f32 from XLenFVT for RV32.

We don't expect this to be used on RV32 currently so remove it
to reduce number of entries in the isel table.

Teach RegisterInfoEmitter.cpp to allow a type to be missing for
a particular HwMode.