[all-commits] [llvm/llvm-project] 208fc3: [RISCV] Improve SiFive7 for reductions and ordered...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 208fc34c65d648e869d7d3ba0dfcbca90942cda0
      https://github.com/llvm/llvm-project/commit/208fc34c65d648e869d7d3ba0dfcbca90942cda0
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2023-06-22 (Thu, 22 Jun 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

  Log Message:
  -----------
  [RISCV] Improve SiFive7 for reductions and ordered reductions

Since the scheduling resources for reductions and ordered reductions now
account for LMUL and SEW, we can modify the Latency and ResourceCycles
for these resoruces.

* Most reductions take a total of approx `vl*SEW/DLEN + 5*(4 + log2(DLEN/SEW))`
  cycles.
* Ordered floating-point reductions take a total of approx `5*vl` cycles.

Differential Revision: https://reviews.llvm.org/D153474