[all-commits] [llvm/llvm-project] ecef87: [RISCV] Improve SiFive7 for loads and stores

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ecef87b2a2675fa86e06f88b69b3f98b7822aedc
      https://github.com/llvm/llvm-project/commit/ecef87b2a2675fa86e06f88b69b3f98b7822aedc
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2023-06-22 (Thu, 22 Jun 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

  Log Message:
  -----------
  [RISCV] Improve SiFive7 for loads and stores

* Unit-stride loads and stores can operate at the full bandwidth of the
memory pipe. The memory pipe is DLEN bits wide.

* Strided loads and stores operate at one element per cycle and should
be scheduled accordingly.

* Indexed loads and stores operate at one element per cycle, and they
stall the machine until all addresses have been generated, so they
cannot be scheduled.

* Unit stride seg2 load is number of DLEN parts

* seg3-8 are one segment per cycle, unless the segment is larger
than DLEN in which each segment takes multiple cycles.

Differential Revision: https://reviews.llvm.org/D153475