[all-commits] [llvm/llvm-project] 9ed668: [RISCV] Model vxrm control for vsmul, vssra, vssrl...
Yueh-Ting (eop) Chen via All-commits
all-commits at lists.llvm.org
Tue Jun 20 11:09:40 PDT 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 9ed668ad93218ab2fe062c977d89f486056b4e56
https://github.com/llvm/llvm-project/commit/9ed668ad93218ab2fe062c977d89f486056b4e56
Author: eopXD <yueh.ting.chen at gmail.com>
Date: 2023-06-20 (Tue, 20 Jun 2023)
Changed paths:
M clang/include/clang/Basic/riscv_vector.td
M clang/lib/Sema/SemaChecking.cpp
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vnclip-out-of-range.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vnclipu-out-of-range.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-out-of-range.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vssra-out-of-range.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vssrl-out-of-range.c
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
M llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
M llvm/test/CodeGen/RISCV/rvv/vnclip.ll
M llvm/test/CodeGen/RISCV/rvv/vnclipu.ll
M llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll
Log Message:
-----------
[RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu
Depends on D151397.
This patch follows the patch-set of D151395. This patch seeks to
update all the remaining fixed-point intrinsics to model vxrm
control, adding rounding mode control for `vsmul`, `vssra`,
`vssrl`, `vnclip`, and `vnclipu`.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D152879
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