[all-commits] [llvm/llvm-project] 5510f0: [3/3][RISCV][POC] Model vxrm in C intrinsics for R...

[Yueh-Ting (eop) Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5510f0b8f4b1400905194f0c75acb41c6b1c21ce
      https://github.com/llvm/llvm-project/commit/5510f0b8f4b1400905194f0c75acb41c6b1c21ce
  Author: eopXD <yueh.ting.chen at gmail.com>
  Date:   2023-06-20 (Tue, 20 Jun 2023)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    M clang/lib/Sema/SemaChecking.cpp
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaadd-out-of-range.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaaddu-out-of-range.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vasub-out-of-range.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vasubu-out-of-range.c
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
    M llvm/test/CodeGen/RISCV/rvv/vaadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vaaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/vasub.ll
    M llvm/test/CodeGen/RISCV/rvv/vasubu.ll

  Log Message:
  -----------
  [3/3][RISCV][POC] Model vxrm in C intrinsics for RVV fixed-point instruction vaadd, vasub

Depends on D151396.

This is the 3rd patch of the patch-set. For the cover letter of the
patch-set, please checkout D151395.

This commit consists of change in both clang front-end and RISC-
back-end.

In the front-end, this commit adds an additional operand to the C
intrinsics of `vaadd`, `vaaddu`, `vasub`, and `vasubu`, that models
the control of the rounding mode.

In the back-end, using `vaadd` as an example, this commit replaces the
existing `int.riscv.vaadd.*` with `int.riscv.vaadd.rm.*` that was
introduced in the previous patch, with the extra operand that models
the control of the rounding mode (`vxrm`) for RVV fixed-point
intrinsics.

Note: The first 3 commit of the patch-set shows the intent to model the
rounding mode for fixed-point intrinsics by applying change to
`vaadd`, `vaaddu`, `vasub`, and `vasubu`. The proceeding patch will
apply the change to the rest of the other fixed-point instructions.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D151397