[all-commits] [llvm/llvm-project] 80fe31: [mlir][sparse] add support for direct prod/and/min...

[Aart Bik via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 80fe3168b507587cd9db47115de609d98188c6f5
      https://github.com/llvm/llvm-project/commit/80fe3168b507587cd9db47115de609d98188c6f5
  Author: Aart Bik <ajcbik at google.com>
  Date:   2023-06-12 (Mon, 12 Jun 2023)

  Changed paths:
    M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp
    A mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reductions_min.mlir

  Log Message:
  -----------
  [mlir][sparse] add support for direct prod/and/min/max reductions

We recently fixed a bug in "sparsifying" such reductions, since
it incorrectly changed this into reductions over stored elements
only , which only works for add/sub/or/xor. However, we still want
to be able to "sparsify" the reductions even in the general case,
and this is a first step by rewriting them into a custom reduction
that feeds in the implicit zeros. NOTE HOWEVER, that in the long run
we want to do this better and feed in any implicit zero only ONCE
for efficiency.

Reviewed By: Peiming

Differential Revision: https://reviews.llvm.org/D152580