[all-commits] [llvm/llvm-project] d33910: [AArch64][SME2/SVE2p1] Add predicate-as-counter in...

[sdesmalen-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d33910a8cc838587886a7302e7f8e6761bb5a89c
      https://github.com/llvm/llvm-project/commit/d33910a8cc838587886a7302e7f8e6761bb5a89c
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2023-05-22 (Mon, 22 May 2023)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsAArch64.td
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
    A llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx2.ll
    A llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx4.ll

  Log Message:
  -----------
  [AArch64][SME2/SVE2p1] Add predicate-as-counter intrinsics for sel

These intrinsics are used to implement the sel intrinsics that selects
a tuple of 2 or 4 values based on a predicate-as-counter operand, e.g.

  __attribute__((arm_streaming))
  svuint8x2_t svsel[_u8_x2](svcount_t png, svuint8x2_t zn, svuint8x2_t zm);

  __attribute__((arm_streaming))
  svuint8x4_t svsel[_u8_x4](svcount_t png, svuint8x4_t zn, svuint8x4_t zm);

As described in https://github.com/ARM-software/acle/pull/217

Reviewed By: CarolineConcatto

Differential Revision: https://reviews.llvm.org/D150951


  Commit: 387c49f693c82bdf8b9b0f1ef48a92f51bb781b4
      https://github.com/llvm/llvm-project/commit/387c49f693c82bdf8b9b0f1ef48a92f51bb781b4
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2023-05-22 (Mon, 22 May 2023)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsAArch64.td
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    A llvm/test/CodeGen/AArch64/sve2p1-intrinsics-loads.ll
    A llvm/test/CodeGen/AArch64/sve2p1-intrinsics-stores.ll

  Log Message:
  -----------
  [AArch64][SME2/SVE2p1] Add predicate-as-counter intrinsics for ld1/ldnt1/st1/stnt1

These intrinsics are used to implement multi-vector load/store intrinsics that loads
or stores a tuple of 2 or 4 values, based on a predicate-as-counter operand, e.g.

  __attribute__((arm_streaming))
  svuint8x2_t svld1[_u8]_x2(svcount_t png, const uint8_t *rn);

  __attribute__((arm_streaming))
  void svst1[_u8_x2](svcount_t png, uint8_t *rn, svuint8x2_t zt);

As described in https://github.com/ARM-software/acle/pull/217

Reviewed By: CarolineConcatto

Differential Revision: https://reviews.llvm.org/D150956


Compare: https://github.com/llvm/llvm-project/compare/50f0ee8fbfc1...387c49f693c8