[all-commits] [llvm/llvm-project] 728b8a: [RISCV] Make zve32f imply F and zve64d imply D.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 728b8a139804db4fd9bce1ac7fa3dcbaf4dc316c
      https://github.com/llvm/llvm-project/commit/728b8a139804db4fd9bce1ac7fa3dcbaf4dc316c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-05-06 (Sat, 06 May 2023)

  Changed paths:
    M clang/test/Driver/riscv-arch.c
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td

  Log Message:
  -----------
  [RISCV] Make zve32f imply F and zve64d imply D.

The 1.0 vector spec PDF has text that says that Zve32f is compatible
with F or Zfinx and that Zve64d is compatible with D and Zdinx.
The references to *inx were removed from the spec in the github repository in
October 2021. The 1.0 pdf was made in September 2021.

Relevant commit https://github.com/riscv/riscv-v-spec/commit/6fedb869e213da03f36092d661d14911a2f9d2c6

Reviewed By: jacquesguan

Differential Revision: https://reviews.llvm.org/D150021