[all-commits] [llvm/llvm-project] e12428: [clang-format] Recognize Verilog edge identifiers

[eywdck2l via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e12428557a4545c0bd1b277dac2d5b56cae3c156
      https://github.com/llvm/llvm-project/commit/e12428557a4545c0bd1b277dac2d5b56cae3c156
  Author: sstwcw <f0gukp2nk at protonmail.com>
  Date:   2023-05-07 (Sun, 07 May 2023)

  Changed paths:
    M clang/lib/Format/FormatToken.h
    M clang/unittests/Format/FormatTestVerilog.cpp
    M clang/unittests/Format/TokenAnnotatorTest.cpp

  Log Message:
  -----------
  [clang-format] Recognize Verilog edge identifiers

Previously the event expression would be misidentified as a port list.
A line break would be added after the comma.  The events can be
separated with either a comma or the `or` keyword, and a line break
would not be inserted if the `or` keyword was used.  We changed the
behavior of the comma to match the `or` keyword.

Before:
```
always @(posedge x,
         posedge y)
  x <= x;
always @(posedge x or posedge y)
  x <= x;
```

After:
```
always @(posedge x, posedge y)
  x <= x;
always @(posedge x or posedge y)
  x <= x;
```

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D149561


  Commit: df722b01246de56a1d3c6f5b1e7aaa881c39f642
      https://github.com/llvm/llvm-project/commit/df722b01246de56a1d3c6f5b1e7aaa881c39f642
  Author: sstwcw <f0gukp2nk at protonmail.com>
  Date:   2023-05-07 (Sun, 07 May 2023)

  Changed paths:
    M clang/lib/Format/ContinuationIndenter.cpp
    M clang/unittests/Format/FormatTestVerilog.cpp

  Log Message:
  -----------
  [clang-format] Don't indent Verilog `begin` keyword on its own line

When the line is too long and the `begin` keyword wraps to the next
line, it shouldn't be indented.

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D149657


Compare: https://github.com/llvm/llvm-project/compare/e5f0f1d3ee95...df722b01246d