[all-commits] [llvm/llvm-project] 139f67: [AArch64] Remove dead tryMLAV64LaneV128 and tryMUL...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 139f678c7849d90eff715da99d80bbb8b75a79a5
      https://github.com/llvm/llvm-project/commit/139f678c7849d90eff715da99d80bbb8b75a79a5
  Author: David Green <david.green at arm.com>
  Date:   2023-04-19 (Wed, 19 Apr 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    A llvm/test/CodeGen/AArch64/sve-pr62151.ll

  Log Message:
  -----------
  [AArch64] Remove dead tryMLAV64LaneV128 and tryMULLV64LaneV128 code.

As far as I can tell this code is never used, as the pattern recognised by
checkHighLaneIndex (an duplane with insert_subvec and extract_subvec) will not
be generated any more. There are no tests that change from removing it
(including the clang neon tests), and it didn't appear to come up in any
benchmarks I ran. There are already existing tablegen patterns for MLA with
index and s/umull with index.

Removing it also prevents it from causing problems for SVE, as in #62151.

Differential Revision: https://reviews.llvm.org/D148646