[all-commits] [llvm/llvm-project] 164b04: [RISCV] Convert segment registers to VR registers ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 164b046ebfa8d7ad36ce567e2214c97e4e7b1657
      https://github.com/llvm/llvm-project/commit/164b046ebfa8d7ad36ce567e2214c97e4e7b1657
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-03-22 (Wed, 22 Mar 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVMCInstLower.cpp

  Log Message:
  -----------
  [RISCV] Convert segment registers to VR registers in RISCVMCInstLower.

Similar to what we do for the LMUL>1 register classes. The printing
is only working today because the segment registers have "ABI" names
set to their base register name.


  Commit: a67e989cd2a730ea778102f2a0d965daed0182bd
      https://github.com/llvm/llvm-project/commit/a67e989cd2a730ea778102f2a0d965daed0182bd
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-03-22 (Wed, 22 Mar 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td

  Log Message:
  -----------
  [RISCV] Add FallbackRegAltNameIndex to ABIRegAltName.

Remove now redundant fake ABI names from vector registers.

This also fixes a crash that occurs if you use fflags as an instruction
operand in the assembly and use -debug. It's not a valid register
for any instruction since this wouldn't be common. It doesn't have
an ABI name so it crashes the register printing in the debug output.


Compare: https://github.com/llvm/llvm-project/compare/9e3ca7987a4d...a67e989cd2a7