[all-commits] [llvm/llvm-project] 0d94b6: [IR] Add LLVM IR support for target("aarch64.svcou...

[sdesmalen-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0d94b636048c240ad31cc0dfffb3cfbec821c83d
      https://github.com/llvm/llvm-project/commit/0d94b636048c240ad31cc0dfffb3cfbec821c83d
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2023-03-01 (Wed, 01 Mar 2023)

  Changed paths:
    M llvm/docs/AArch64SME.rst
    M llvm/lib/IR/Type.cpp
    A llvm/test/Transforms/InstCombine/AArch64/sme-svcount.ll
    A llvm/test/Transforms/SROA/aarch64-sme-svcount.ll

  Log Message:
  -----------
  [IR] Add LLVM IR support for target("aarch64.svcount") type.

The C and C++ Language Extensions for AArch64 SME2 [1] adds a new type called
`svcount_t` which describes a predicate. This is not a predicate vector
mask, but rather a description of a predicate vector mask that can be
expanded into a mask using explicit instructions. The type is a scalable
opaque type.

To implement `svcount_t` type this patch uses the existing Target Extension Type
mechanism, but adds further support so that this type can be a scalable type.

AArch64 CodeGen support will follow in a separate patch.

[1] https://github.com/ARM-software/acle/pull/217

Reviewed By: jcranmer-intel, nikic

Differential Revision: https://reviews.llvm.org/D136861