[all-commits] [llvm/llvm-project] f62622: [RISCV] Add vendor-defined XTheadMemIdx (Indexed M...
Philipp Tomsich via All-commits
all-commits at lists.llvm.org
Thu Feb 23 15:18:16 PST 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: f6262201d8fd52260c205f7426cb22b18ee06ac7
https://github.com/llvm/llvm-project/commit/f6262201d8fd52260c205f7426cb22b18ee06ac7
Author: Manolis Tsamis <manolis.tsamis at vrull.eu>
Date: 2023-02-24 (Fri, 24 Feb 2023)
Changed paths:
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.rst
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
M llvm/test/CodeGen/RISCV/attributes.ll
A llvm/test/CodeGen/RISCV/xtheadmemidx.ll
A llvm/test/MC/RISCV/rv32xtheadmemidx-invalid.s
A llvm/test/MC/RISCV/rv32xtheadmemidx-valid.s
A llvm/test/MC/RISCV/rv64xtheadmemidx-invalid.s
A llvm/test/MC/RISCV/rv64xtheadmemidx-valid.s
Log Message:
-----------
[RISCV] Add vendor-defined XTheadMemIdx (Indexed Memory Operations) extension
The vendor-defined XTHeadMemIdx (no comparable standard extension exists
at the time of writing) extension adds indexed load/store instructions
as well as load/store and update register instructions.
It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for this
extension is available at:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=27cfd142d0a7e378d19aa9a1278e2137f849b71b
Depends on D144002
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D144249
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