[all-commits] [llvm/llvm-project] 73cd3d: [LSR] Prevent creating SCEVs of addrecs from misma...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 73cd3d4391ad47ae72028d4d01df0865b033dfed
      https://github.com/llvm/llvm-project/commit/73cd3d4391ad47ae72028d4d01df0865b033dfed
  Author: David Green <david.green at arm.com>
  Date:   2023-02-22 (Wed, 22 Feb 2023)

  Changed paths:
    M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
    A llvm/test/CodeGen/X86/lsr-addrecloops.ll

  Log Message:
  -----------
  [LSR] Prevent creating SCEVs of addrecs from mismatching loops

LSR can include Regs of AddRec SCEVs from different loops, which do not combine
well when added in Scalar Evolution. As they should never produce constant
differences so we can just guard against trying to create them.

Fixes #60927