[all-commits] [llvm/llvm-project] bbb58a: [RISCV] Add vendor-defined XTheadMemPair (two-GPR ...

[Philipp Tomsich via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bbb58a2302c65b73943e00f2def3384a68177a7f
      https://github.com/llvm/llvm-project/commit/bbb58a2302c65b73943e00f2def3384a68177a7f
  Author: Manolis Tsamis <manolis.tsamis at vrull.eu>
  Date:   2023-02-21 (Tue, 21 Feb 2023)

  Changed paths:
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    A llvm/test/CodeGen/RISCV/xtheadmempair.ll
    A llvm/test/MC/RISCV/rv32xtheadmempair-invalid.s
    A llvm/test/MC/RISCV/rv32xtheadmempair-valid.s
    A llvm/test/MC/RISCV/rv64xtheadmempair-invalid.s
    A llvm/test/MC/RISCV/rv64xtheadmempair-valid.s

  Log Message:
  -----------
  [RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension

The vendor-defined XTHeadMemPair (no comparable standard extension exists
at the time of writing) extension adds two-GPR load/store pair instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=6e17ae625570ff8f3c12c8765b8d45d4db8694bd

Depends on D143847

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144002