[all-commits] [llvm/llvm-project] a942a9: [X86] Improve (select carry C1+1 C1)

[kazutakahirata via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a942a944245374fc62a5af8ee3abbc579f5ee7a5
      https://github.com/llvm/llvm-project/commit/a942a944245374fc62a5af8ee3abbc579f5ee7a5
  Author: Kazu Hirata <kazu at google.com>
  Date:   2023-02-20 (Mon, 20 Feb 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/select_const.ll

  Log Message:
  -----------
  [X86] Improve (select carry C1+1 C1)

Without this patch:

  return X < 4 ? 3 : 2;

  return X < 9 ? 7 : 6;

are compiled as:

  31 c0                   xor    %eax,%eax
  83 ff 04                cmp    $0x4,%edi
  0f 93 c0                setae  %al
  83 f0 03                xor    $0x3,%eax

  31 c0                   xor    %eax,%eax
  83 ff 09                cmp    $0x9,%edi
  0f 92 c0                setb   %al
  83 c8 06                or     $0x6,%eax

respectively.  With this patch, we generate:

  31 c0                   xor    %eax,%eax
  83 ff 04                cmp    $0x4,%edi
  83 d0 02                adc    $0x2,%eax

  31 c0                   xor    %eax,%eax
  83 ff 04                cmp    $0x4,%edi
  83 d0 02                adc    $0x2,%eax

respectively, saving 3 bytes while reducing the tree height.

This patch recognizes the equivalence of OR and ADD
(if bits do not overlap) and delegates to combineAddOrSubToADCOrSBB
for further processing.  The same applies to the equivalence of XOR
and SUB.

Differential Revision: https://reviews.llvm.org/D143838