[all-commits] [llvm/llvm-project] c6c672: [AArch64] More consistently use buildvector for ze...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c6c6723189f40b0ea823925bd616ff1bdb0eccf3
      https://github.com/llvm/llvm-project/commit/c6c6723189f40b0ea823925bd616ff1bdb0eccf3
  Author: David Green <david.green at arm.com>
  Date:   2023-02-20 (Mon, 20 Feb 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/build-one-lane.ll
    M llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll
    M llvm/test/CodeGen/AArch64/urem-vector-lkk.ll
    M llvm/test/CodeGen/AArch64/vecreduce-add-legalization.ll
    M llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll

  Log Message:
  -----------
  [AArch64] More consistently use buildvector for zero and all-ones constants

The AArch64 backend will use legal BUILDVECTORs for zero vectors or all-ones
vectors, so during selection tablegen patterns get rely on immAllZerosV and
immAllOnesV pattern frags in patterns like vnot. It was not always consistent
though, which this patch attempt to fix by recognizing where constant splat +
insert vector element is used. The main outcome of this will be that full
vector movi v0.2d, #0000000000000000 will be used as opposed to movi d0, #0, as
per https://reviews.llvm.org/D53579. This helps simplify what tablegen will
see, to make pattern matching simpler.

Differential Revision: https://reviews.llvm.org/D144018