[all-commits] [llvm/llvm-project] 16a66a: Revert "[RISCV] Add vendor-defined XTheadMemPair (...

[Philipp Tomsich via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 16a66af0a0fed21b13100afc9cff89db7235ea20
      https://github.com/llvm/llvm-project/commit/16a66af0a0fed21b13100afc9cff89db7235ea20
  Author: Philipp Tomsich <philipp.tomsich at vrull.eu>
  Date:   2023-02-17 (Fri, 17 Feb 2023)

  Changed paths:
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    R llvm/test/CodeGen/RISCV/xtheadmempair.ll
    R llvm/test/MC/RISCV/rv32xtheadmempair-invalid.s
    R llvm/test/MC/RISCV/rv32xtheadmempair-valid.s
    R llvm/test/MC/RISCV/rv64xtheadmempair-invalid.s
    R llvm/test/MC/RISCV/rv64xtheadmempair-valid.s

  Log Message:
  -----------
  Revert "[RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension"

This reverts commit d2918544a7fc4b5443879fe12f32a712e6dfe325.


  Commit: efe7c4b77bed76ef3af6fd018122b428c21512b7
      https://github.com/llvm/llvm-project/commit/efe7c4b77bed76ef3af6fd018122b428c21512b7
  Author: Philipp Tomsich <philipp.tomsich at vrull.eu>
  Date:   2023-02-17 (Fri, 17 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

  Log Message:
  -----------
  Revert "[RISCV] Add performMULcombine to perform strength-reduction"

This reverts commit 20cc23c708f04ca3fbc4289a68302a4b684ce448.


Compare: https://github.com/llvm/llvm-project/compare/6774ba841145...efe7c4b77bed