[all-commits] [llvm/llvm-project] d29185: [RISCV] Add vendor-defined XTheadMemPair (two-GPR ...

[Philipp Tomsich via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d2918544a7fc4b5443879fe12f32a712e6dfe325
      https://github.com/llvm/llvm-project/commit/d2918544a7fc4b5443879fe12f32a712e6dfe325
  Author: Manolis Tsamis <manolis.tsamis at vrull.eu>
  Date:   2023-02-17 (Fri, 17 Feb 2023)

  Changed paths:
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    A llvm/test/CodeGen/RISCV/xtheadmempair.ll
    A llvm/test/MC/RISCV/rv32xtheadmempair-invalid.s
    A llvm/test/MC/RISCV/rv32xtheadmempair-valid.s
    A llvm/test/MC/RISCV/rv64xtheadmempair-invalid.s
    A llvm/test/MC/RISCV/rv64xtheadmempair-valid.s

  Log Message:
  -----------
  [RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension

The vendor-defined XTHeadMemPair (no comparable standard extension exists
at the time of writing) extension adds two-GPR load/store pair instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=6e17ae625570ff8f3c12c8765b8d45d4db8694bd

Depends on D143847

Differential Revision: https://reviews.llvm.org/D144002


  Commit: 20cc23c708f04ca3fbc4289a68302a4b684ce448
      https://github.com/llvm/llvm-project/commit/20cc23c708f04ca3fbc4289a68302a4b684ce448
  Author: Philipp Tomsich <philipp.tomsich at vrull.eu>
  Date:   2023-02-17 (Fri, 17 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

  Log Message:
  -----------
  [RISCV] Add performMULcombine to perform strength-reduction

The RISC-V backend thus far does not provide strength-reduction, which
causes a long (but not complete) list of 3-instruction patterns listed
to utilize the shift-and-add instruction from Zba and XTHeadBa in
strength-reduction.

This adds the logic to perform strength-reduction through the DAG
combine for ISD::MUL.  Initially, we wire this up for XTheadBa only,
until this has had some time to settle and get real-world test
exposure.

The following strength-reductions strategies are currently supported:
  - XTheadBa
    - C = (n + 1)           // th.addsl
    - C = (n + 1)k          // th.addsl, slli
    - C = (n + 1)(m + 1)    // th.addsl, th.addsl
    - C = (n + 1)(m + 1)k   // th.addsl, th.addsl, slli
    - C = ((n + 1)m + 1)    // th.addsl, th.addsl
    - C = ((n + 1)m + 1)k   // th.addslm th.addsl, slli
  - base ISA
    - C being 2 set-bits    // slli, slli, add
			       (possibly slli, th.addsl)

Even though the slli+slli+add sequence would we supported without
XTheadBa, this currently is gated to avoid having to update a large
number of test cases (i.e., anything that has a multiplication with a
constant where only 2 bits are set) in this commit.

With the strength reduction now being performed in performMUL combine,
we drop the (now redundant) patterns from RISCVInstrInfoXTHead.td.

Depends on D143029

Differential Revision: https://reviews.llvm.org/D143394


  Commit: 6774ba841145195c490531bcbfe334b338ec779b
      https://github.com/llvm/llvm-project/commit/6774ba841145195c490531bcbfe334b338ec779b
  Author: Manolis Tsamis <manolis.tsamis at vrull.eu>
  Date:   2023-02-17 (Fri, 17 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    A llvm/test/CodeGen/RISCV/bitextract-mac.ll
    M llvm/test/CodeGen/RISCV/xtheadmac.ll

  Log Message:
  -----------
  [RISCV] xtheadmac: fix commutativity issue for the in/out register

The instructions in the XTHeadMac extension (multiply accumulate
instructions) were marked as commutative but because the destination
register was also an input (accumulate) register and was connected to
the destination register with a register allocator constraint, all
three operands (instead of two) were incorrectly considered
commutative. To fix that an appropriate fixCommutedOpIndices call was
added for these instructions in findCommutedOpIndices

New test functions have been added to test the correct behaviour in
xtheadmac.ll.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144278


Compare: https://github.com/llvm/llvm-project/compare/21a543656cf4...6774ba841145