[all-commits] [llvm/llvm-project] d2fd0d: [RISCV] Simplify some code in RISCVDisassembler. NFC

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d2fd0d3cbc2e3fbd813189e0342fa78d3a0e7057
      https://github.com/llvm/llvm-project/commit/d2fd0d3cbc2e3fbd813189e0342fa78d3a0e7057
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-02-05 (Sun, 05 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

  Log Message:
  -----------
  [RISCV] Simplify some code in RISCVDisassembler. NFC

Create X0 register directly instead of passing 0 to DecodeGPRRegisterClass.


  Commit: 3a606785c5c4e60e3882f2486165e0b07a37de3b
      https://github.com/llvm/llvm-project/commit/3a606785c5c4e60e3882f2486165e0b07a37de3b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-02-05 (Sun, 05 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

  Log Message:
  -----------
  [RISCV] Use uint32_t intead of uint64_t for instruction fields in RISCVDisassembler.cpp. NFC

The tablegen generated code is templated based on the type of Insn
passed to decodeInstruction which is currently uint32_t. All of the
fields extracted will this type.


Compare: https://github.com/llvm/llvm-project/compare/be3f4591aff0...3a606785c5c4