[all-commits] [llvm/llvm-project] cad708: [clang-format] Recognize Verilog non-blocking assi...

[eywdck2l via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cad708b9a1ecbf5645706056bb7c4fc0ea4721b6
      https://github.com/llvm/llvm-project/commit/cad708b9a1ecbf5645706056bb7c4fc0ea4721b6
  Author: sstwcw <f0gukp2nk at protonmail.com>
  Date:   2023-02-06 (Mon, 06 Feb 2023)

  Changed paths:
    M clang/lib/Format/TokenAnnotator.cpp
    M clang/lib/Format/WhitespaceManager.cpp
    M clang/unittests/Format/FormatTestVerilog.cpp
    M clang/unittests/Format/TokenAnnotatorTest.cpp

  Log Message:
  -----------
  [clang-format] Recognize Verilog non-blocking assignment

Reviewed By: HazardyKnusperkeks, owenpan

Differential Revision: https://reviews.llvm.org/D142891