[all-commits] [llvm/llvm-project] c469f5: [RISCV] Remove fimmneg0 patterns that were replace...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c469f57124ae176aa439c5b15e49f8d170826ac4
      https://github.com/llvm/llvm-project/commit/c469f57124ae176aa439c5b15e49f8d170826ac4
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-02-04 (Sat, 04 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

  Log Message:
  -----------
  [RISCV] Remove fimmneg0 patterns that were replaced by D142953.


  Commit: 301db4f920014a157162ccb2756a4ad02a53f040
      https://github.com/llvm/llvm-project/commit/301db4f920014a157162ccb2756a4ad02a53f040
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-02-04 (Sat, 04 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

  Log Message:
  -----------
  [RISCV] Use MVT enum directly instead of converting to bit width. NFC


  Commit: 65ece07e0222b090c35686a91af5b161acc0f8e3
      https://github.com/llvm/llvm-project/commit/65ece07e0222b090c35686a91af5b161acc0f8e3
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-02-04 (Sat, 04 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

  Log Message:
  -----------
  [RISCV] Replace condition that should alwasy be true with an assert. NFC


  Commit: fe6dd5d3115987622907f7541314a2fe163eb57b
      https://github.com/llvm/llvm-project/commit/fe6dd5d3115987622907f7541314a2fe163eb57b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-02-04 (Sat, 04 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

  Log Message:
  -----------
  [RISCV] Make selectImm return SDValue instead of SDNode*.

This avoids multiple places needing to convert it to SDValue. It's
simpler to convert it to SDNode * in the places that need it.


  Commit: 712e143883d694d3b5817dae714da2315eae8c89
      https://github.com/llvm/llvm-project/commit/712e143883d694d3b5817dae714da2315eae8c89
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-02-04 (Sat, 04 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll

  Log Message:
  -----------
  [RISCV] Fix crash splatting f64 -0.0 into a vector on RV32 after D142953.

For RV32, we now use scalar fcvt of x0, scalar fneg, splat scalar fp to vector.
For RV64, we use li of 1, slli by 63, splat GPR to vector.


Compare: https://github.com/llvm/llvm-project/compare/3c7a7a7b46f0...712e143883d6