[all-commits] [llvm/llvm-project] 8f25e3: [X86] Add basic vector handling for ISD::ABDS/ABDU...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8f25e382c5b1bbaafd738f44de856c85ce845bbe
      https://github.com/llvm/llvm-project/commit/8f25e382c5b1bbaafd738f44de856c85ce845bbe
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-02-04 (Sat, 04 Feb 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/abds-vector-128.ll
    M llvm/test/CodeGen/X86/abds-vector-256.ll
    M llvm/test/CodeGen/X86/abds-vector-512.ll
    M llvm/test/CodeGen/X86/abdu-vector-128.ll
    M llvm/test/CodeGen/X86/abdu-vector-256.ll
    M llvm/test/CodeGen/X86/abdu-vector-512.ll
    M llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
    M llvm/test/CodeGen/X86/midpoint-int-vec-512.ll

  Log Message:
  -----------
  [X86] Add basic vector handling for ISD::ABDS/ABDU (absolute difference) nodes

I'm intending to add generic legalization in the future, but for now I've added basic support to targets that have the necessary MIN/MAX support to expand to SUB(MAX(X,Y),MIN(X,Y)).

This exposed a couple of issues with the DAG combines - in particular we need to catch trunc(abs(sub(ext(x),ext(y)))) patterns earlier before the SSE/AVX vector trunc expansion folds trigger.

Differential Revision: https://reviews.llvm.org/D142288