[all-commits] [llvm/llvm-project] 57a6bb: [AArch64][SME2] Add multi-vector zip/uzp intrinsics

[david-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 57a6bb34729df30df18a133ee2083b3323a936dc
      https://github.com/llvm/llvm-project/commit/57a6bb34729df30df18a133ee2083b3323a936dc
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2023-02-03 (Fri, 03 Feb 2023)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsAArch64.td
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    A llvm/test/CodeGen/AArch64/sve2p1-intrinsics-uzpx2.ll
    A llvm/test/CodeGen/AArch64/sve2p1-intrinsics-uzpx4.ll
    A llvm/test/CodeGen/AArch64/sve2p1-intrinsics-zipx2.ll
    A llvm/test/CodeGen/AArch64/sve2p1-intrinsics-zipx4.ll

  Log Message:
  -----------
  [AArch64][SME2] Add multi-vector zip/uzp intrinsics

This patch adds the LLVM IR intrinsics for the following:

* zip (2 and 4 vectors, 8 to 64-bit elements) - aarch64.sve.zip.*
* zip (2 and 4 vectors, 128-bit elements) - aarch64.sve.zipq.*
* uzp (2 and 4 vectors, 8 to 64-bit elements) - aarch64.sve.uzp.*
* uzp (2 and 4 vectors, 128-bit elements) - aarch64.sve.uzpq.*

I have created separate intrinsics for the 128-bit variants
in a similar way to what was done for int_aarch64_sme_readq_horiz.
This permits us to use any vector type (<vscale x 16 x i8>, etc.)
for the 128-bit versions.

I have also named the tests sve2p1-intrinsics-* because although
the instructions are added as part of the SME2 feature they only
operate on SVE vectors.

NOTE: These intrinsics are still in development and are subject to future changes.

Differential Revision: https://reviews.llvm.org/D142904