[all-commits] [llvm/llvm-project] 4b43ef: [PowerPC] Switch to by-name matching for instructi...

[James Y Knight via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4b43ef3e5c37459996ce0f53615881f436cb0e65
      https://github.com/llvm/llvm-project/commit/4b43ef3e5c37459996ce0f53615881f436cb0e65
  Author: James Y Knight <jyknight at google.com>
  Date:   2023-02-02 (Thu, 02 Feb 2023)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
    M llvm/lib/Target/PowerPC/PPCInstrAltivec.td
    M llvm/lib/Target/PowerPC/PPCInstrFormats.td
    M llvm/lib/Target/PowerPC/PPCInstrFuture.td
    M llvm/lib/Target/PowerPC/PPCInstrHTM.td
    M llvm/lib/Target/PowerPC/PPCInstrInfo.td
    M llvm/lib/Target/PowerPC/PPCInstrMMA.td
    M llvm/lib/Target/PowerPC/PPCInstrP10.td
    M llvm/lib/Target/PowerPC/PPCInstrSPE.td
    M llvm/lib/Target/PowerPC/PPCInstrVSX.td
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.td

  Log Message:
  -----------
  [PowerPC] Switch to by-name matching for instructions (part 1 of 2).

This is a follow-on to https://reviews.llvm.org/D134073.

After https://reviews.llvm.org/D137653 we can now switch the PPC
target away from positional operand matching.

This patch fixes all of the "easy" cases. While this changes a large
number of lines of tablegen source, it results in only a single
non-comment change in the code generated by tablegen: the (unused)
codegen-only "MTVRSAVEv" instruction was previously incorrectly
encoding operand 0, and now encodes (correctly) operand 1.

Changes which result in generated-code changes have been split off
into the next (smaller) patch, for ease of review.

Reviewed By: barannikov88

Differential Revision: https://reviews.llvm.org/D137661


  Commit: 0be684ed97397ef06c1ba391df0cf84b87edb792
      https://github.com/llvm/llvm-project/commit/0be684ed97397ef06c1ba391df0cf84b87edb792
  Author: James Y Knight <jyknight at google.com>
  Date:   2023-02-02 (Thu, 02 Feb 2023)

  Changed paths:
    M llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h
    M llvm/lib/Target/PowerPC/PPC.td
    M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
    M llvm/lib/Target/PowerPC/PPCInstrFormats.td
    M llvm/lib/Target/PowerPC/PPCInstrInfo.td
    M llvm/lib/Target/PowerPC/PPCInstrP10.td
    M llvm/lib/Target/PowerPC/PPCInstrSPE.td
    M llvm/lib/Target/PowerPC/PPCInstrVSX.td
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.td

  Log Message:
  -----------
  [PowerPC] Switch to by-name matching for instructions (part 2 of 2).

This is a follow-on to https://reviews.llvm.org/D134073.

Currently, all of the "memri"-style complex operands, which contain
both a register and an immediate, are encoded into a single field in
the instruction definition. This requires complex encoders/decoders,
and instruction definitions that insert and extract the correct parts
of the bits.

Now, switch to naming and encoding/decoding the sub-operands
separately.

Thus, we can now disable useDeprecatedPositionallyEncodedOperands.

Reviewed By: barannikov88

Differential Revision: https://reviews.llvm.org/D137670


Compare: https://github.com/llvm/llvm-project/compare/9fe7d38e240a...0be684ed9739