[all-commits] [llvm/llvm-project] 84b6d0: [RISCV] Move the even register check for rv32zdinx...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 84b6d074d7dc4474e259d2f535cb53901a03008c
      https://github.com/llvm/llvm-project/commit/84b6d074d7dc4474e259d2f535cb53901a03008c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-02-01 (Wed, 01 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/test/MC/RISCV/rv32zdinx-invalid.s
    M llvm/test/MC/RISCV/rv32zfinx-invalid.s
    M llvm/test/MC/RISCV/rv64zdinx-valid.s

  Log Message:
  -----------
  [RISCV] Move the even register check for rv32zdinx later in the matching process.

And remove the IsRV64 checks for isGPRAsFPR and isGPRPF64AsFPR.

Overall I think this results in a better diagnostic experience. We
now do a better job of matching Zdinx instructions even if the registers
aren't correct and report an error for missing features like RV64.

Unfortunately, this makes it difficult to recover the error location
for the invalid odd register when we do report it. But to make up
for it, I gave a more specific error message.

It doesn't look like binutils gives any warning or error for odd registers.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D142997