[all-commits] [llvm/llvm-project] a2f453: Transform slow LEA_B_I_D/LEA_SLOWBASE_I -> LEA_IS_...

[goldsteinn via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a2f45348d4ea93434d166ab9c6f73a28dba18595
      https://github.com/llvm/llvm-project/commit/a2f45348d4ea93434d166ab9c6f73a28dba18595
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2023-02-01 (Wed, 01 Feb 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86FixupLEAs.cpp
    M llvm/test/CodeGen/X86/leaFixup32.mir
    M llvm/test/CodeGen/X86/leaFixup64.mir
    M llvm/test/CodeGen/X86/select-1-or-neg1.ll
    M llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir

  Log Message:
  -----------
  Transform slow LEA_B_I_D/LEA_SLOWBASE_I -> LEA_IS_D/LEA_IS iff base == index

The two 3c LEA cases:
    lea D(base, index,1)      -> lea D(,index,2)
    lea D(r13/rbp, index)     -> lea D(,r13/rbp,2) // D maybe zero

Current take 2 instructions to transform. We can do a bit better by
using LEA w.o a base if base == index and scale == 1.

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D141980


  Commit: c68caff2e9b1ed28b5e7df68de6dd70b0ca2da4b
      https://github.com/llvm/llvm-project/commit/c68caff2e9b1ed28b5e7df68de6dd70b0ca2da4b
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2023-02-01 (Wed, 01 Feb 2023)

  Changed paths:
    M llvm/test/CodeGen/X86/switch-bt.ll

  Log Message:
  -----------
  Use autogenerated result for switch-bt.ll test; NFC

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D142860


  Commit: c05ddc9cbc12b1f2038380f57a16c4ca98c614b7
      https://github.com/llvm/llvm-project/commit/c05ddc9cbc12b1f2038380f57a16c4ca98c614b7
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2023-02-01 (Wed, 01 Feb 2023)

  Changed paths:
    M llvm/lib/CodeGen/BranchFolding.cpp
    M llvm/test/CodeGen/X86/add.ll
    M llvm/test/CodeGen/X86/atom-pad-short-functions.ll
    M llvm/test/CodeGen/X86/avx512-i1test.ll
    M llvm/test/CodeGen/X86/bmi.ll
    M llvm/test/CodeGen/X86/brcond.ll
    M llvm/test/CodeGen/X86/btq.ll
    M llvm/test/CodeGen/X86/cmp-merge.ll
    M llvm/test/CodeGen/X86/cmp.ll
    M llvm/test/CodeGen/X86/comi-flags.ll
    M llvm/test/CodeGen/X86/extern_weak.ll
    M llvm/test/CodeGen/X86/fold-rmw-ops.ll
    M llvm/test/CodeGen/X86/fp-strict-scalar-cmp-fp16.ll
    M llvm/test/CodeGen/X86/fp-strict-scalar-cmp.ll
    M llvm/test/CodeGen/X86/funnel-shift.ll
    M llvm/test/CodeGen/X86/jump_sign.ll
    M llvm/test/CodeGen/X86/neg_cmp.ll
    M llvm/test/CodeGen/X86/or-branch.ll
    M llvm/test/CodeGen/X86/peep-test-4.ll
    M llvm/test/CodeGen/X86/pr37025.ll
    M llvm/test/CodeGen/X86/pr37063.ll
    M llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll
    M llvm/test/CodeGen/X86/segmented-stacks.ll
    M llvm/test/CodeGen/X86/sibcall.ll
    M llvm/test/CodeGen/X86/slow-incdec.ll
    M llvm/test/CodeGen/X86/sqrt-partial.ll
    M llvm/test/CodeGen/X86/switch-bt.ll
    M llvm/test/CodeGen/X86/tail-opts.ll
    M llvm/test/CodeGen/X86/tailcall-cgp-dup.ll
    M llvm/test/CodeGen/X86/tailcall-extract.ll
    M llvm/test/CodeGen/X86/xor-icmp.ll

  Log Message:
  -----------
  Improve and enable folding of conditional branches with tail calls.

Improve and enable folding of conditional branches with tail calls.

1. Make it so that conditional tail calls can be emitted even when
   there are multiple predecessors.

2. Don't guard the transformation behind -Os. The rationale for
   guarding it was static-prediction can be affected by whether the
   branch is forward of backward. This is no longer true for almost any
   X86 cpus (anything newer than `SnB`) so is no longer a meaningful
   concern.

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D140931


  Commit: 95e49f5a74c9e79778a62cc58b15875613cf9e59
      https://github.com/llvm/llvm-project/commit/95e49f5a74c9e79778a62cc58b15875613cf9e59
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2023-02-01 (Wed, 01 Feb 2023)

  Changed paths:
    M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
    A llvm/test/MC/X86/prefetchit-non-rip-op.s

  Log Message:
  -----------
  Make `prefetchit{0/1}` emit an assembler warning if the operand is not rip-rel

Without a rip-rel operand, `prefetchit{0/1}` is a nop. This is a
reasonable mistake for someone to make and is almost certainly not
what they are after.

This matches the same warning in `gas`.

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D142797


Compare: https://github.com/llvm/llvm-project/compare/e1af75572d3a...95e49f5a74c9