[all-commits] [llvm/llvm-project] d3ddbe: [mlir][vector] Clarify vector.contract promotion b...

[Lei Zhang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d3ddbe153e4ce1377653c8fb2936334bf9d105cf
      https://github.com/llvm/llvm-project/commit/d3ddbe153e4ce1377653c8fb2936334bf9d105cf
  Author: Lei Zhang <antiagainst at google.com>
  Date:   2023-01-31 (Tue, 31 Jan 2023)

  Changed paths:
    M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
    M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
    M mlir/test/Dialect/Vector/invalid.mlir

  Log Message:
  -----------
  [mlir][vector] Clarify vector.contract promotion behavior

This commit updates vector.contract documentation to clarify
the promotion behavior if operands and the result have different
bitwidths. It also adds a check to disable signed/unsigned integer
types and only allow signless integers.

Reviewed By: ThomasRaoux

Differential Revision: https://reviews.llvm.org/D142915