[all-commits] [llvm/llvm-project] 86eff6: [MachineCombiner] Use default latency model when n...
Philip Reames via All-commits
all-commits at lists.llvm.org
Fri Jan 20 09:28:38 PST 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 86eff6be686a1e41e13c08ebfc2db4dd4d58e7c6
https://github.com/llvm/llvm-project/commit/86eff6be686a1e41e13c08ebfc2db4dd4d58e7c6
Author: Philip Reames <preames at rivosinc.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M llvm/lib/CodeGen/MachineCombiner.cpp
M llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll
M llvm/test/CodeGen/RISCV/addcarry.ll
M llvm/test/CodeGen/RISCV/addimm-mulimm.ll
M llvm/test/CodeGen/RISCV/alu64.ll
M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/div-by-constant.ll
M llvm/test/CodeGen/RISCV/div-pow2.ll
M llvm/test/CodeGen/RISCV/div.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/iabs.ll
M llvm/test/CodeGen/RISCV/mul.ll
M llvm/test/CodeGen/RISCV/neg-abs.ll
M llvm/test/CodeGen/RISCV/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rvv/expand-no-v.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
M llvm/test/CodeGen/RISCV/sadd_sat.ll
M llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/select-binop-identity.ll
M llvm/test/CodeGen/RISCV/shadowcallstack.ll
M llvm/test/CodeGen/RISCV/shifts.ll
M llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll
M llvm/test/CodeGen/RISCV/srem-lkk.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/ssub_sat.ll
M llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
M llvm/test/CodeGen/RISCV/uadd_sat.ll
M llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/RISCV/unaligned-load-store.ll
M llvm/test/CodeGen/RISCV/urem-lkk.ll
M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/usub_sat.ll
M llvm/test/CodeGen/RISCV/usub_sat_plus.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
M llvm/test/CodeGen/X86/abdu-vector-128.ll
M llvm/test/CodeGen/X86/add-sub-bool.ll
M llvm/test/CodeGen/X86/alias-static-alloca.ll
M llvm/test/CodeGen/X86/avx-vinsertf128.ll
M llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll
M llvm/test/CodeGen/X86/avx512-intrinsics-x86_64.ll
M llvm/test/CodeGen/X86/avx512-intrinsics.ll
M llvm/test/CodeGen/X86/avx512-mask-op.ll
M llvm/test/CodeGen/X86/avx512-regcall-Mask.ll
M llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
M llvm/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
M llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll
M llvm/test/CodeGen/X86/avx512fp16-mov.ll
M llvm/test/CodeGen/X86/avx512fp16-mscatter.ll
M llvm/test/CodeGen/X86/avx512vl-intrinsics.ll
M llvm/test/CodeGen/X86/bmi-out-of-order.ll
M llvm/test/CodeGen/X86/combine-add.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
M llvm/test/CodeGen/X86/divide-by-constant.ll
M llvm/test/CodeGen/X86/divmod128.ll
M llvm/test/CodeGen/X86/fold-add.ll
M llvm/test/CodeGen/X86/fold-masked-merge.ll
M llvm/test/CodeGen/X86/fold-tied-op.ll
M llvm/test/CodeGen/X86/h-registers-1.ll
M llvm/test/CodeGen/X86/hipe-cc.ll
M llvm/test/CodeGen/X86/hipe-cc64.ll
M llvm/test/CodeGen/X86/horizontal-reduce-add.ll
M llvm/test/CodeGen/X86/horizontal-reduce-fadd.ll
M llvm/test/CodeGen/X86/horizontal-reduce-smax.ll
M llvm/test/CodeGen/X86/horizontal-reduce-smin.ll
M llvm/test/CodeGen/X86/horizontal-reduce-umax.ll
M llvm/test/CodeGen/X86/horizontal-reduce-umin.ll
M llvm/test/CodeGen/X86/horizontal-sum.ll
M llvm/test/CodeGen/X86/icmp-shift-opt.ll
M llvm/test/CodeGen/X86/imul.ll
M llvm/test/CodeGen/X86/lea-opt-cse4.ll
M llvm/test/CodeGen/X86/lea-opt2.ll
M llvm/test/CodeGen/X86/logic-shift.ll
M llvm/test/CodeGen/X86/machine-cp.ll
M llvm/test/CodeGen/X86/madd.ll
M llvm/test/CodeGen/X86/masked_gather.ll
M llvm/test/CodeGen/X86/masked_gather_scatter.ll
M llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll
M llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
M llvm/test/CodeGen/X86/midpoint-int.ll
M llvm/test/CodeGen/X86/movmsk-cmp.ll
M llvm/test/CodeGen/X86/mul-constant-i64.ll
M llvm/test/CodeGen/X86/mul-constant-result.ll
M llvm/test/CodeGen/X86/mul-i1024.ll
M llvm/test/CodeGen/X86/mul-i256.ll
M llvm/test/CodeGen/X86/mul-i512.ll
M llvm/test/CodeGen/X86/mul128.ll
M llvm/test/CodeGen/X86/mul64.ll
M llvm/test/CodeGen/X86/muloti.ll
M llvm/test/CodeGen/X86/optimize-max-0.ll
M llvm/test/CodeGen/X86/popcnt.ll
M llvm/test/CodeGen/X86/pr34080-2.ll
M llvm/test/CodeGen/X86/ptest.ll
M llvm/test/CodeGen/X86/rev16.ll
M llvm/test/CodeGen/X86/rotate-multi.ll
M llvm/test/CodeGen/X86/sad.ll
M llvm/test/CodeGen/X86/setcc-wide-types.ll
M llvm/test/CodeGen/X86/shift-combine.ll
M llvm/test/CodeGen/X86/smul-with-overflow.ll
M llvm/test/CodeGen/X86/smul_fix.ll
M llvm/test/CodeGen/X86/smul_fix_sat.ll
M llvm/test/CodeGen/X86/smulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/X86/sse-regcall.ll
M llvm/test/CodeGen/X86/stack-clash-large.ll
M llvm/test/CodeGen/X86/statepoint-live-in.ll
M llvm/test/CodeGen/X86/statepoint-regs.ll
M llvm/test/CodeGen/X86/swift-return.ll
M llvm/test/CodeGen/X86/umul-with-overflow.ll
M llvm/test/CodeGen/X86/umul_fix.ll
M llvm/test/CodeGen/X86/umul_fix_sat.ll
M llvm/test/CodeGen/X86/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/X86/umulo-64-legalisation-lowering.ll
M llvm/test/CodeGen/X86/urem-seteq-nonzero.ll
M llvm/test/CodeGen/X86/v8i1-masks.ll
M llvm/test/CodeGen/X86/vec_smulo.ll
M llvm/test/CodeGen/X86/vec_umulo.ll
M llvm/test/CodeGen/X86/vector-fshr-128.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-pcmp.ll
M llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
M llvm/test/CodeGen/X86/vector-reduce-add-sext.ll
M llvm/test/CodeGen/X86/vector-reduce-add-zext.ll
M llvm/test/CodeGen/X86/vector-reduce-add.ll
M llvm/test/CodeGen/X86/vector-reduce-and-bool.ll
M llvm/test/CodeGen/X86/vector-reduce-and-cmp.ll
M llvm/test/CodeGen/X86/vector-reduce-and.ll
M llvm/test/CodeGen/X86/vector-reduce-mul.ll
M llvm/test/CodeGen/X86/vector-reduce-or-bool.ll
M llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
M llvm/test/CodeGen/X86/vector-reduce-or.ll
M llvm/test/CodeGen/X86/vector-reduce-smax.ll
M llvm/test/CodeGen/X86/vector-reduce-smin.ll
M llvm/test/CodeGen/X86/vector-reduce-umax.ll
M llvm/test/CodeGen/X86/vector-reduce-umin.ll
M llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
M llvm/test/CodeGen/X86/vector-reduce-xor.ll
M llvm/test/CodeGen/X86/vector-trunc-math.ll
M llvm/test/CodeGen/X86/vector-trunc-packus.ll
M llvm/test/CodeGen/X86/vp2intersect_multiple_pairs.ll
M llvm/test/CodeGen/X86/win-smallparams.ll
M llvm/test/CodeGen/X86/x86-32-vector-calling-conv.ll
M llvm/test/CodeGen/X86/x86-interleaved-access.ll
M llvm/test/CodeGen/X86/x86-no_caller_saved_registers-preserve.ll
M llvm/test/CodeGen/X86/xmulo.ll
Log Message:
-----------
[MachineCombiner] Use default latency model when no detailed model available
This change adjusts the cost modeling used when the target does not have a schedule model with individual instruction latencies. After this change, we use the default latency information available from TargetSchedule. The default latency information essentially ends up treating most instructions as latency 1, with a few "expensive" ones getting a higher cost.
Previously, we unconditionally applied the first legal pattern - without any consideration of profitability. As a result, this change both prevents some patterns being applied, and changes which patterns are exercised. (i.e. previously the first pattern was applied, afterwards, maybe the second one is because the first wasn't profitable.)
The motivation here is two fold.
First, this brings the default behavior in line with the behavior when -mcpu or -mtune is specified. This improves test coverage, and generally makes it less likely we will have bad surprises when providing more information to the compiler.
Second, this enables some reassociation for ILP by default. Despite being unconditionally enabled, the prior code tended to "reassociate" repeatedly through an entire chain and simply moving the first operand to the end. The result was still a serial chain, just a different one. With this change, one of the intermediate transforms is unprofitable and we end up with a partially flattened tree.
Note that the resulting code diffs show significant room for improvement in the basic algorithm. I am intentionally excluding those from this patch.
For the test diffs, I don't seen any concerning regressions. I took a fairly close look at the RISCV ones, but only skimmed the x86 (particularly vector x86) changes.
Differential Revision: https://reviews.llvm.org/D141017
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