[all-commits] [llvm/llvm-project] 2ad4c3: clang: Fix handling of __builtin_elementwise_copysign

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2ad4c3c88d884684a3efb42181e87fe305df51bd
      https://github.com/llvm/llvm-project/commit/2ad4c3c88d884684a3efb42181e87fe305df51bd
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2023-01-10 (Tue, 10 Jan 2023)

  Changed paths:
    M clang/lib/Sema/SemaChecking.cpp
    M clang/test/CodeGen/builtins-elementwise-math.c
    M clang/test/Sema/builtins-elementwise-math.c

  Log Message:
  -----------
  clang: Fix handling of __builtin_elementwise_copysign

I realized the handling of copysign made no sense at all.
Only the type of the first operand should really matter, and
it should not perform a conversion between them.

Also fixes misleading errors and producing broken IR for
integers.

We could accept different FP types for the sign argument,
if the intrinsic permitted different types like the DAG node.
As it is we would need to insert a cast, which could have
other effects (like trapping on snan) which should not happen
for a copysign.


  Commit: 6454391b3111993f277fb2570d28f59699b7dae2
      https://github.com/llvm/llvm-project/commit/6454391b3111993f277fb2570d28f59699b7dae2
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2023-01-10 (Tue, 10 Jan 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/br-constant-invalid-sgpr-copy.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll

  Log Message:
  -----------
  AMDGPU/GlobalISel: Widen s1 SGPR constants during regbankselect

To unambiguously interpret these as 32-bit SGPRs, we need to widen
these to s32. This was selecting to a copy from a 64-bit SGPR to a
32-bit SGPR for wave64.


Compare: https://github.com/llvm/llvm-project/compare/10410534696e...6454391b3111