[all-commits] [llvm/llvm-project] 90f24b: [ARM] Fold And/Or into CSel if possible

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 90f24bef47227d58f2ccdcc481ca22eff32248ca
      https://github.com/llvm/llvm-project/commit/90f24bef47227d58f2ccdcc481ca22eff32248ca
  Author: David Green <david.green at arm.com>
  Date:   2023-01-09 (Mon, 09 Jan 2023)

  Changed paths:
    M llvm/lib/Target/ARM/ARMInstrInfo.td
    M llvm/lib/Target/ARM/ARMInstrThumb2.td
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
    M llvm/test/CodeGen/Thumb2/csel-andor-onebit.ll
    M llvm/test/CodeGen/Thumb2/mve-nounrolledremainder.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-and.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-or.ll
    M llvm/test/CodeGen/Thumb2/mve-vcmp.ll
    M llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
    M llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
    M llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
    M llvm/test/CodeGen/Thumb2/mve-vcmpr.ll

  Log Message:
  -----------
  [ARM] Fold And/Or into CSel if possible

This is the ARM equivalent of D141119, where we fold `and x, (csel 0, 1, cc)`
to `csel ZR, x, cc` if we know that x is 0/1 and for `or x, (csel 0, 1, cc)`
emit `csinc x, ZR, cc`. The or pattern gets recognized from a cmov under Arm.

Differential Revision: https://reviews.llvm.org/D141137