[all-commits] [llvm/llvm-project] 248016: [NFC][Codegen][x86] Add tests for load/store of a ...

[Roman Lebedev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2480164247c970e130f3f59c9d8498c12a078deb
      https://github.com/llvm/llvm-project/commit/2480164247c970e130f3f59c9d8498c12a078deb
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2022-12-31 (Sat, 31 Dec 2022)

  Changed paths:
    A llvm/test/CodeGen/X86/single_elt_vector_memory_operation.ll

  Log Message:
  -----------
  [NFC][Codegen][x86] Add tests for load/store of a single-element vectors


  Commit: 16facf1ca60c5f1118e32bca4219d9c233dfaf28
      https://github.com/llvm/llvm-project/commit/16facf1ca60c5f1118e32bca4219d9c233dfaf28
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2022-12-31 (Sat, 31 Dec 2022)

  Changed paths:
    M llvm/lib/CodeGen/TargetLoweringBase.cpp
    M llvm/test/CodeGen/AArch64/merge-store.ll
    M llvm/test/CodeGen/X86/single_elt_vector_memory_operation.ll
    M llvm/test/CodeGen/X86/widen_load-0.ll

  Log Message:
  -----------
  [DAGCombiner][TLI] Do not fuse bitcast to <1 x ?> into a load/store of a vector

Single-element vectors are legalized by splitting,
so the the memory operations would also get scalarized.
While we do have some support to reconstruct scalarized loads,
we clearly don't catch everything.

The comment for the affected AArch64 store suggests that
having two stores was the desired outcome in the first place.

This was showing as a source of *many* regressions
with more aggressive ZERO_EXTEND_VECTOR_INREG recognition.


Compare: https://github.com/llvm/llvm-project/compare/603e8490729e...16facf1ca60c