[all-commits] [llvm/llvm-project] e50976: [RISCV] Teach RISCVDAGToDAGISel::selectShiftMask t...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e50976e56933c3e907246e01deb14b5dd485032b
      https://github.com/llvm/llvm-project/commit/e50976e56933c3e907246e01deb14b5dd485032b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-12-29 (Thu, 29 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/alu64.ll
    M llvm/test/CodeGen/RISCV/rotl-rotr.ll
    M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/rv32zbs.ll
    M llvm/test/CodeGen/RISCV/shift-masked-shamt.ll
    M llvm/test/CodeGen/RISCV/shifts.ll
    M llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
    M llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll

  Log Message:
  -----------
  [RISCV] Teach RISCVDAGToDAGISel::selectShiftMask to bypass adds with constant.

If the shift amount is (add X, C) where C is 0 modulo the size of
the shift, we can bypass the add.

Similar to other targets like AArch64 and X86.