[all-commits] [llvm/llvm-project] 821a59: [TwoAddressInstruction] Constrain RegClass when pr...

Danila Malyutin via All-commits all-commits at lists.llvm.org
Mon Dec 26 08:01:11 PST 2022

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 821a59588b5bddb1fe092291910ecf2744e1e49f
  Author: Danila Malyutin <dmalyutin at azul.com>
  Date:   2022-12-26 (Mon, 26 Dec 2022)

  Changed paths:
    M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
    A llvm/test/CodeGen/AArch64/statepoint-twoaddr.mir

  Log Message:
  [TwoAddressInstruction] Constrain RegClass when processing a statepoint

This transformation could've triggered a verifier assert if RegA and RegB
were of different reg classes. Fix this by constraining as the comment
for replaceRegWith suggests.

Differential Revision: https://reviews.llvm.org/D140672

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