[all-commits] [llvm/llvm-project] 8c618e: [Xtensa 1/10] Recognize Xtensa in triple parsing code
Stefan Stipanovic via All-commits
all-commits at lists.llvm.org
Mon Dec 26 04:38:56 PST 2022
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 8c618e8f53b166818e4465405fae676efb4cb1b2
https://github.com/llvm/llvm-project/commit/8c618e8f53b166818e4465405fae676efb4cb1b2
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2022-12-26 (Mon, 26 Dec 2022)
Changed paths:
M llvm/CODE_OWNERS.TXT
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/TargetParser/Triple.cpp
M llvm/unittests/TargetParser/TripleTest.cpp
Log Message:
-----------
[Xtensa 1/10] Recognize Xtensa in triple parsing code
I'm sharing initial set of patches that adds LLVM backend for Xtensa architecture.
It is based on this LLVM fork https://github.com/espressif/llvm-xtensa.
I prepared patches by similar way like it was already successfully done for RISCV, i.e. incrementally add an initial MC layer for Xtensa by small chunks which could be reviewable.
Differential Revision: https://reviews.llvm.org/D64826
Commit: 310f7652f7961fa8178937c7c928d7f629c8253a
https://github.com/llvm/llvm-project/commit/310f7652f7961fa8178937c7c928d7f629c8253a
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2022-12-26 (Mon, 26 Dec 2022)
Changed paths:
M llvm/include/llvm/BinaryFormat/ELF.h
A llvm/include/llvm/BinaryFormat/ELFRelocs/Xtensa.def
M llvm/include/llvm/Object/ELFObjectFile.h
M llvm/include/llvm/module.modulemap
M llvm/lib/Object/ELF.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/test/Object/obj2yaml.test
A llvm/test/tools/llvm-readobj/ELF/reloc-types-xtensa.test
A llvm/test/tools/llvm-readobj/ELF/xtensa-header-flags.test
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/unittests/Object/ELFObjectFileTest.cpp
Log Message:
-----------
[Xtensa 2/10] Add Xtensa ELF definitions
Add file with Xtensa ELF relocations. Add Xtensa support to ELF.h,
ELFObject.h and ELFYAML.cpp. Add simple test of Xtensa ELF representation in YAML.
Differential Revision: https://reviews.llvm.org/D64827
Commit: 52804a7f22a20e020caacb71571e0cca712f0a12
https://github.com/llvm/llvm-project/commit/52804a7f22a20e020caacb71571e0cca712f0a12
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2022-12-26 (Mon, 26 Dec 2022)
Changed paths:
A llvm/lib/Target/Xtensa/CMakeLists.txt
A llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h
A llvm/lib/Target/Xtensa/TargetInfo/CMakeLists.txt
A llvm/lib/Target/Xtensa/TargetInfo/XtensaTargetInfo.cpp
A llvm/lib/Target/Xtensa/TargetInfo/XtensaTargetInfo.h
A llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
A llvm/lib/Target/Xtensa/XtensaTargetMachine.h
Log Message:
-----------
[Xtensa 3/10] Add initial version of the Xtensa backend
Add Xtensa MCTargetDesc stub. Add XtensaTargetMachine and XtensaTargetInfo.
Modify llib/Target/LLVMBuild.txt. Now Xtensa target could be builded as EXPERIMENTAL.
Differential Revision: https://reviews.llvm.org/D64829
Commit: 8a6552016c97ae3c1e4fe6d18a1f5ac43a4a44c1
https://github.com/llvm/llvm-project/commit/8a6552016c97ae3c1e4fe6d18a1f5ac43a4a44c1
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2022-12-26 (Mon, 26 Dec 2022)
Changed paths:
M llvm/lib/Target/Xtensa/CMakeLists.txt
A llvm/lib/Target/Xtensa/Xtensa.td
A llvm/lib/Target/Xtensa/XtensaInstrFormats.td
A llvm/lib/Target/Xtensa/XtensaInstrInfo.td
A llvm/lib/Target/Xtensa/XtensaOperands.td
A llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
Log Message:
-----------
[Xtensa 4/10] Add basic *td files with Xtensa architecture description
Add initial Xtensa.td file with target machine description. Add XtensaInstrInfo.td,
currently describe just susbet of Core Instructions like ALU, Processor control,
memory barrier and some move instructions. Add descriptions of the instructions
formats(XtensaInstrInfo.td) and some immediate instruction operands(XtensaOperands.td).
Add General Registers and Special Registers classes.
Differential Revision: https://reviews.llvm.org/D64830
Commit: 6017209760c61f95ebc531d398f42a68e3fc9313
https://github.com/llvm/llvm-project/commit/6017209760c61f95ebc531d398f42a68e3fc9313
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2022-12-26 (Mon, 26 Dec 2022)
Changed paths:
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/Target/Xtensa/CMakeLists.txt
M llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaELFObjectWriter.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCAsmInfo.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCAsmInfo.h
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h
M llvm/lib/Target/Xtensa/XtensaOperands.td
Log Message:
-----------
[Xtensa 5/10] Add Xtensa MCTargetDescr initial functionality
Differential Revision: https://reviews.llvm.org/D64831
Commit: 52ecf023ed2430ba6d6c9804869184458b01f4ce
https://github.com/llvm/llvm-project/commit/52ecf023ed2430ba6d6c9804869184458b01f4ce
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2022-12-26 (Mon, 26 Dec 2022)
Changed paths:
A llvm/lib/Target/Xtensa/AsmParser/CMakeLists.txt
A llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/CMakeLists.txt
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h
M llvm/lib/Target/Xtensa/Xtensa.td
Log Message:
-----------
[Xtensa 6/10] Add Xtensa basic assembler parser
Currently parse just described in *.td files Xtensa instructions and operands subsets.
Differential Revision: https://reviews.llvm.org/D64832
Commit: 2758a01395148790377af95606c623405b08f0e6
https://github.com/llvm/llvm-project/commit/2758a01395148790377af95606c623405b08f0e6
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2022-12-26 (Mon, 26 Dec 2022)
Changed paths:
M llvm/lib/Target/Xtensa/CMakeLists.txt
M llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
M llvm/lib/Target/Xtensa/Xtensa.td
A llvm/test/MC/Xtensa/Core/arith.s
A llvm/test/MC/Xtensa/Core/invalid.s
A llvm/test/MC/Xtensa/Core/memorder.s
A llvm/test/MC/Xtensa/Core/move.s
A llvm/test/MC/Xtensa/Core/processor-control.s
A llvm/test/MC/Xtensa/Misc/elf-header.s
A llvm/test/MC/Xtensa/lit.local.cfg
Log Message:
-----------
[Xtensa 7/10] Add Xtensa instruction printer
Add printer for current instructions and operands subsets.
Also add basic tests of the Xtensa instructions.
Differential Revision: https://reviews.llvm.org/D64833
Commit: 4e0c1d98d3717d10e0230604a088ef38a3f7e060
https://github.com/llvm/llvm-project/commit/4e0c1d98d3717d10e0230604a088ef38a3f7e060
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2022-12-26 (Mon, 26 Dec 2022)
Changed paths:
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperands.td
M llvm/test/MC/Xtensa/Core/invalid.s
A llvm/test/MC/Xtensa/Core/memory.s
M llvm/test/MC/Xtensa/Core/move.s
M llvm/test/MC/Xtensa/Core/processor-control.s
A llvm/test/MC/Xtensa/Core/shift.s
Log Message:
-----------
[Xtensa 8/10] Add support of the Xtensa shift/load/store/move and processor control instructions
Add new subset of Core Instructions (not full yet). Add appropriate operands description,
modify asm parser, printer and code emitter. Modify tests to support new instructions.
Differential Revision: https://reviews.llvm.org/D64834
Commit: 71199af14c578a72a5c0fec6ecaa5eab1645a7b7
https://github.com/llvm/llvm-project/commit/71199af14c578a72a5c0fec6ecaa5eab1645a7b7
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2022-12-26 (Mon, 26 Dec 2022)
Changed paths:
M llvm/lib/Target/Xtensa/CMakeLists.txt
A llvm/lib/Target/Xtensa/Disassembler/CMakeLists.txt
A llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/XtensaOperands.td
Log Message:
-----------
[Xtensa 9/10] Add basic support of Xtensa disassembler
Differential Revision: https://reviews.llvm.org/D64835
Commit: ff25800d4ba0b577a44dc918da7a1fb3c29fdb13
https://github.com/llvm/llvm-project/commit/ff25800d4ba0b577a44dc918da7a1fb3c29fdb13
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2022-12-26 (Mon, 26 Dec 2022)
Changed paths:
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaELFObjectWriter.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaFixupKinds.h
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCExpr.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCExpr.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperands.td
A llvm/test/MC/Xtensa/Core/branch.s
A llvm/test/MC/Xtensa/Core/call-jump.s
M llvm/test/MC/Xtensa/Core/invalid.s
A llvm/test/MC/Xtensa/Relocations/fixups-diagnostics.s
A llvm/test/MC/Xtensa/Relocations/fixups.s
A llvm/test/MC/Xtensa/Relocations/relocations.s
Log Message:
-----------
[Xtensa 10/10] Add relaxations and fixups. Add rest part of Xtensa Core Instructions
Add branch/jump/call/l32r instructions and fixups support. Add R_XTENSA_32/R_XTENSA_SLOT0_OP
relocations in object files generation. Modify tests to support new instructions.
Add tests for relocations and fixups.
Differential Revision: https://reviews.llvm.org/D64836
Compare: https://github.com/llvm/llvm-project/compare/77fad4c31e9c...ff25800d4ba0
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