[all-commits] [llvm/llvm-project] 132546: [RISCV] Add DAG combine to fold (select C, (add X, ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 132546d9397c062d4b2f50fac76392a11d3d6f27
      https://github.com/llvm/llvm-project/commit/132546d9397c062d4b2f50fac76392a11d3d6f27
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-12-21 (Wed, 21 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
    M llvm/test/CodeGen/RISCV/select.ll
    M llvm/test/CodeGen/RISCV/sextw-removal.ll

  Log Message:
  -----------
  [RISCV] Add DAG combine to fold (select C, (add X, Y), Y) -> (add (select C, X, 0), Y).

Similar for sub, or, and xor. These are all operations that have 0
as a neutral value. This is based on a similar tranform in InstCombine.

This allows us to remove some XVentanaCondOps patterns and
some code from DAGCombine for RISCVISD::SELECT_CC.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D140465