[all-commits] [llvm/llvm-project] 673b4a: [AArch64] Add FP16 instructions to isAssociativeAn...

[KAWASHIMA Takahiro via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 673b4ad64577e3336cb8109869919b21341e0d74
      https://github.com/llvm/llvm-project/commit/673b4ad64577e3336cb8109869919b21341e0d74
  Author: KAWASHIMA Takahiro <t-kawashima at fujitsu.com>
  Date:   2022-12-20 (Tue, 20 Dec 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/test/CodeGen/AArch64/machine-combiner.ll

  Log Message:
  -----------
  [AArch64] Add FP16 instructions to isAssociativeAndCommutative

`-mcpu=` in `llvm/test/CodeGen/AArch64/machine-combiner.ll` is changed
to `neoverse-n2` to use FP16 and SVE/SVE2 instructions. By this, the
register allocation and/or instruction scheduling are slightly changed
and some existing `CHECK` lines need to be updated.

Differential Revision: https://reviews.llvm.org/D139809


  Commit: 347d2be7bef3a49b7dbe19ff1f964c1c3fb2999f
      https://github.com/llvm/llvm-project/commit/347d2be7bef3a49b7dbe19ff1f964c1c3fb2999f
  Author: KAWASHIMA Takahiro <t-kawashima at fujitsu.com>
  Date:   2022-12-20 (Tue, 20 Dec 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/test/CodeGen/AArch64/machine-combiner.ll
    M llvm/test/CodeGen/AArch64/reduce-shuffle.ll

  Log Message:
  -----------
  [AArch64] Add Neon int instructions to isAssociativeAndCommutative

Differential Revision: https://reviews.llvm.org/D139810


Compare: https://github.com/llvm/llvm-project/compare/4ac51dd53d93...347d2be7bef3