[all-commits] [llvm/llvm-project] 454997: [AAch64] Optimize muls with operands having enough...

[bipmis via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 454997d3965936ebc813d4bea5e3a639fb0e7cb4
      https://github.com/llvm/llvm-project/commit/454997d3965936ebc813d4bea5e3a639fb0e7cb4
  Author: bipmis <biplob.mishra at arm.com>
  Date:   2022-12-20 (Tue, 20 Dec 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
    M llvm/test/CodeGen/AArch64/addcarry-crash.ll

  Log Message:
  -----------
  [AAch64] Optimize muls with operands having enough zero bits.

Muls with 64bit operands where each of the operand is having top 32 bits as zero, we can generate a single umull instruction on a 32bit operand.

Differential Revision: https://reviews.llvm.org/D139411