[all-commits] [llvm/llvm-project] 3c0c24: [AArch64] Combine to UMULL if top bits are known zero

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3c0c24e0c1d37e903eab484b34ef854ec785346b
      https://github.com/llvm/llvm-project/commit/3c0c24e0c1d37e903eab484b34ef854ec785346b
  Author: David Green <david.green at arm.com>
  Date:   2022-12-20 (Tue, 20 Dec 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
    M llvm/test/CodeGen/AArch64/aarch64-smull.ll

  Log Message:
  -----------
  [AArch64] Combine to UMULL if top bits are known zero

Given mul(zext(a), b), we can convert to a umull so long as we know that
the top bits of b are zero. This uses MaskedValueIsZero to detect that
case for NEON UMULL patterns.

Differential Revision: https://reviews.llvm.org/D140287