[all-commits] [llvm/llvm-project] d393d0: [TableGen] Emit table mapping physical registers t...

[Carl Ritson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d393d0d24239aedfd3c8166e7dc188f360104cac
      https://github.com/llvm/llvm-project/commit/d393d0d24239aedfd3c8166e7dc188f360104cac
  Author: Carl Ritson <carl.ritson at amd.com>
  Date:   2022-12-20 (Tue, 20 Dec 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/include/llvm/Target/Target.td
    A llvm/test/TableGen/RegisterInfoEmitter-BaseClassOrder.td
    M llvm/utils/TableGen/CodeGenRegisters.h
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  [TableGen] Emit table mapping physical registers to base classes

Allow targets to define a mapping from registers to register
classes such that each register has exactly one base class.
As registers may be in multiple register classes the base class
is determined by the container class with the lowest BaseClassOrder.

Only register classes with BaseClassOrder set are considered
when determining the base classes.  By default BaseClassOrder is
unset in RegisterClass so no code is generated unless a target
explicit defines one or more base register classes.

Reviewed By: arsenm, foad

Differential Revision: https://reviews.llvm.org/D139616