[all-commits] [llvm/llvm-project] 36179e: [RISCV] Replace i64:$r in tablegen patterns with G...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 36179ec2187a8cff935d57b6fc2d1a7585b99fcd
      https://github.com/llvm/llvm-project/commit/36179ec2187a8cff935d57b6fc2d1a7585b99fcd
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-12-19 (Mon, 19 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td

  Log Message:
  -----------
  [RISCV] Replace i64:$r in tablegen patterns with GPR:$r. NFC

It's much more common to use a register class rather than a type.

Add an additional i64 cast to the patterns where needed to avoid
increasing isel table size.